Heterogeneous ALU Architecture -- Power Aware System (2306.15092v1)

Abstract: The advent of heterogeneous multi-core architectures brought with it huge benefits to energy efficiency by running programs on properly-sized cores. Modern heterogeneous multi-core systems as suggested by Artjom et al. schedule tasks to different cores based on governors that may optimize a task for energy use or performance. This provides benefits to the system as a whole in reducing energy costs where possible, but also not compromising on performance for timing-critical applications. In the era of dark silicon, energy optimization is increasingly important, and many architectures have arisen that seek to optimize processors to specific tasks, often at the cost of generality. We propose that we can still achieve energy-saving and potentially performance-improving benefits while not affecting a system's generality at all, by achieving heterogeneity at the level of Arithmetic logic unit (ALUs). Much like a heterogeneous multi-core system achieves benefits from its heterogeneity and efficient scheduling, a heterogeneous ALU system can achieve similar benefits by routing ALU operations to properly sized ALUs. Additionally much like there are scheduling modes for the governors of heterogeneous multi-core processors, we propose that energy-constrained modes can be effective in a heterogeneous ALU system with the routing of operations to smaller ALUs for immense energy savings. We examine the energy and performance characteristics of scaling ripple carry adders and evaluate the total energy and performance benefits of such a system when running applications. With our proposed controls, input operand size-based and energy constraint-based, we could potentially emulate the success of heterogeneous processor task scheduling at a finer-grained level. This paper presents our evaluation of the potential of heterogeneous ALU processors.