Optimized Real-Time Assembly in a RISC Simulator

Simulators for the RISC-V instruction set architecture (ISA) are useful for teaching assembly language and modern CPU architecture concepts. The Assembly/Simulation Platform for Illustration of RISC-V in Education (ASPIRE) is an integrated RISC-V assembler and simulator used to illustrate these concepts and evaluate algorithms to generate machine language code. In this article, ASPIRE is introduced, selected features of the simulator that interactively explain the RISC-V ISA as teaching aides are presented, then two assembly algorithms are evaluated. Both assembly algorithms run in real time as code is being edited in the simulator. The optimized algorithm performs incremental assembly limited to only the portion of the program that is changed. Both algorithms are then evaluated based on overall run-time performance.