Papers
Topics
Authors
Recent
Assistant
AI Research Assistant
Well-researched responses based on relevant abstracts and paper content.
Custom Instructions Pro
Preferences or requirements that you'd like Emergent Mind to consider when generating responses.
Gemini 2.5 Flash
Gemini 2.5 Flash 60 tok/s
Gemini 2.5 Pro 46 tok/s Pro
GPT-5 Medium 23 tok/s Pro
GPT-5 High 30 tok/s Pro
GPT-4o 87 tok/s Pro
Kimi K2 194 tok/s Pro
GPT OSS 120B 460 tok/s Pro
Claude Sonnet 4.5 30 tok/s Pro
2000 character limit reached

Implementation of Digital Circuits on Three-Dimensional FPGAs Using Simulated Annealing (2304.07476v1)

Published 15 Apr 2023 in cs.AR

Abstract: 3D FPGAs have recently been produced as the next generation of the FPGA family to continue the integration of more transistors on a single chip seamlessly. In this paper, we propose a complete CAD flow to implement an arbitrary logic circuit on the 3D FPGA. The partitioning and placement stages of the flow are based on the simulated annealing algorithm. Furthermore, the routing stage is a modified version of the Pathfinder algorithm. The simulation results indicate that the comparison between 2D FPGA and 3D FPGA (including 2-tier) shows that the circuit speed increases by 28.66% and minimum channel width decrease by 29.92%, while the total area raises by 8.86%. Finally, the results of the comparison between 2-tier and 4-tier in 3D FPGA show that circuit speed and minimum channel width increase by 15.95% and 15.92% in 4-tier, respectively. Meanwhile, the total area increases only by 1.96%.

Summary

We haven't generated a summary for this paper yet.

Lightbulb Streamline Icon: https://streamlinehq.com

Continue Learning

We haven't generated follow-up questions for this paper yet.

List To Do Tasks Checklist Streamline Icon: https://streamlinehq.com

Collections

Sign up for free to add this paper to one or more collections.