A 3.3 Gbps SPAD-Based Quantum Random Number Generator

Quantum random number generators are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs there is often little modelling or analytical description of the entropy source, circuit extraction and post-processing provided. In this work, we first discuss theory on the quantum random flip-flop (QRFF), which elucidates the role of circuit imperfections that manifest themselves in bias and correlation. Then, a Verilog-AMS model is developed in order to validate the analytical model in simulation. A novel transistor implementation of the QRFF circuit is presented, which enables compensation of the degradation in entropy inherent to the finite non-symmetric transitions of the random flip-flop. Finally, a full system containing two independent arrays of the QRFF circuit is manufactured and tested in a 55 nm Bipolar-CMOS-DMOS (BCD) technology node, demonstrating bit generation statistics that are commensurate to the developed model. The full chip is able to generate 3.3 Gbps of data when operated with an external LED, whereas an individual QRFF can generate 25 Mbps each of random data while maintaining a Shannon entropy bound > 0.997, which is one of the highest per pixel bit generation rates to date. NIST STS is used to benchmark the generated bit strings, thereby validating the QRFF circuit as an excellent candidate for fully-integrated QRNGs.