Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression

With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance challenges of 2D integration and the memory wall. However, the 3D design of SRAM LLCs has made the thermal problem even more severe. It, therefore, incurs more leakage energy consumption than conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose two different architectures that exploit the data compression to reduce the energy of LLC and interconnects in 3D-ICs.