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Reachability-based Control Synthesis under Signal Temporal Logic Specifications (2110.08019v1)

Published 15 Oct 2021 in eess.SY and cs.SY

Abstract: In this paper, we investigate the controller design problem for linear disturbed systems under signal temporal logic (STL) specifications imposing both spatial and temporal constraints on system behavior. We first implement zonotope-based techniques to partition the state space into finite cells, then propose an evaluation mechanism to rearrange the time constraints of the STL specification, and finally decompose the global STL formula into finite local STL formulas. In this way, each cell has a local control design problem, which is further formulated into a local optimization problem. To deal with each local optimization problem, we take advantage of the properties of zonotopes and reachability analysis to design local controller consisting of feedforward and feedback parts. By solving all local optimization problems, all local controllers are combined to guarantee the global STL specification. Finally, a numerical example is presented to illustrate the derived results.

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