Analytical models of Energy and Throughput for Caches in MPSoCs

General trends in computer architecture are shifting more towards parallelism. Multicore architectures have proven to be a major step in processor evolution. With the advancement in multicore architecture, researchers are focusing on finding different solutions to fully utilize the power of multiple cores. With an ever-increasing number of cores on a chip, the role of cache memory has become pivotal. An ideal memory configuration should be both large and fast, however, in fact, system architects have to strike a balance between the size and access time of the memory hierarchy. It is important to know the impact of a particular cache configuration on the throughput and energy consumption of the system at design time. This paper presents an enhanced version of previously proposed cache energy and throughput models for multicore systems. These models use significantly a smaller number of input parameters as compared to other models. This paper also validates the proposed models through cycle accurate simulator and a renowned processor power estimator. The results show that the proposed energy models provide accuracy within a maximum error range of 10% for single-core processors and around 5% for MPSoCs, and the throughput models result in a maximum error of up to 11.5% for both single and multicore architectures.