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Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding (1405.0413v1)
Published 2 May 2014 in cs.AR, cs.MM, and cs.NA
Abstract: Two multiplierless algorithms are proposed for 4x4 approximate-DCT for transform coding in digital video. Computational architectures for 1-D/2-D realisations are implemented using Xilinx FPGA devices. CMOS synthesis at the 45 nm node indicate real-time operation at 1 GHz yielding 4x4 block rates of 125 MHz at less than 120 mW of dynamic power consumption.